The Flash Memory Farce
In a recent Cambridge A Level Computer Science exam, a question about flash memory awarded marks for saying that flash memory uses two transistors per cell — and that flash memory is actually made from NAND and NOR logic gates. This is not correct. It’s not a simplification. It’s not outdated. It’s wrong, plain and simple.
When I told Cambridge about it, they defended it. That defence tells us everything we need to know about a deeper problem: a qualification and exam board that claims rigour, but reveals that it does not understand the subject it is assessing.
It might seem like a trivial error — but it isn’t. We’ll get into the details in a moment. But first, an analogy...
If you’ve ever watched Spirited Away, you’ll no doubt remember the scene where a “Stink Spirit” enters the bathhouse — oozing sludge, foul-smelling, and seemingly unfixable. Everyone except for Sen recoils. She notices what looks like a thorn sticking out of its side and starts tugging at it. With the help of everyone around her, she finally pulls it free. It’s not a thorn — it’s a bike handle. An entire bicycle emerges, followed by a torrent of garbage and pollution that had built up inside. The spirit wasn’t a Stink Spirit at all. It was a polluted river spirit, buried under years of debris.
This flash memory question was my bike handle moment.
It started as one strange mark scheme answer: awarding full marks for demonstrably false claims about flash memory. But when I started tugging at it, I didn’t just find one isolated mistake — I found a whole plethora of issues. An array of technical misunderstandings, contradictions between guidance materials and examinations, errors in endorsed textbooks, rigid and contradictory examiner behaviour, off-syllabus questions, and a response process that buried its own failures in superficial politeness and anti-intellectualism.
This post tells that story — and what it reveals about Cambridge’s understanding of Computer Science. Are you ready to take the plunge and start tugging?
The Farce Begins
I first noticed the error not in an exam paper, but in one of Cambridge’s endorsed textbooks — Hodder's A Level Computer Science by David Watson and Helen Williams. On page 74, it incorrectly claims that flash memory uses two transistors per cell, stating:
...one transistor is called a floating gate and the other is called a control gate
At the time, I assumed this was just a mistake in the textbook. I became wary of Hodder’s treatment of technical content and began relying on other resources wherever I could.
The Truth About Flash Memory
Flash memory cells use a single type of component: the floating gate transistor (FGT).
This is a special kind of transistor that can “trap” an electrical charge, allowing the cell to represent a binary 1 or 0 depending on whether the charge is present. Each memory cell consists of one floating gate transistor. That’s it.
In reality, the physics and engineering behind flash memory are quite complex. These days, there are variations like charge trap flash, differences in cell types (SLC, MLC, TLC, QLC), and a range of architectural and manufacturing considerations.
But there is no suggestion or hint of a 1 vs. 2 transistor debate.
The fundamental distinction — the innovation that defines flash memory — is that it uses just one transistor per memory cell. This isn’t a minor detail. It’s the reason Fujio Masuoka invented flash memory. It’s what defines the technology and distinguishes it from EEPROM — a different technology that uses two transistors per memory cell.
You might also hear about NAND and NOR in relation to flash memory. These terms don’t refer to NAND or NOR logic gates being used to construct the memory cells. Instead, they describe how the cells are arranged within the memory array:
- NAND flash: transistors are arranged in series - akin to the structure of a NAND gate.
- NOR flash: transistors are arranged in parallel - akin to the structure of a NOR gate.
The naming is reflects architecture, not logic. The cells are still made from floating gate transistors — not from logic gates. This distinction becomes important when we consider the exam paper in question...
The Farce Becomes Official
Not long after noticing the error in the textbook, I saw the exact same misunderstanding repeated in a recent Cambridge A Level exam.
In 9618/11 Paper 1 from the May/June 2024 series, Question 2(c)(ii) asks students to complete a table on the “principal operation of solid state (flash) memory.” One of the entries asks students to state:
The number of transistors contained in each cell
Mark scheme answer: 2
As we have just discussed, this is false. Flash memory cells use one transistor per cell. There is no variant of flash memory, mainstream, niche, historical, or otherwise, that uses two.
The same question also asks students to identify:
The two types of logic gate that can be used to create solid state devices
Mark scheme answer: NAND, NOR
Again, this is demonstrably false. Together, these two items expose a complete misunderstanding of how flash memory actually works. This isn’t a simplification — it’s a fabrication. And Cambridge codified it into an official mark scheme.
The Farce Defended
I raised the issue with Cambridge, and they amended the mark scheme to include the correct answer: “one” transistor per cell. But they also kept “two” as an accepted answer.
In other words: they acknowledged the truth, but refused to let go of the falsehood. This wasn’t a correction. It was a box-ticking exercise — a way to say “we listened” without doing any real self-reflection, taking any responsibility for mistakes, or doing anything that would disturb the self-reinforcing system.
Imagine a Maths exam that asks:
Q: What is 2 + 2?
A: 5 (accepted), 4 (also accepted after complaint)
This isn’t a compromise. It’s academic rot. And the fact that they presented this amendment as evidence of fairness only makes it more concerning. If fairness means rewarding both the correct and an incorrect answer — because enough people repeat the error — then the qualification has ceased to measure real understanding completely.
This is not just a mistake. It’s a failure of academic and professional integrity — and Cambridge has chosen to institutionalise it rather than correct it.
The Farce Cemented
When I presented further evidence to Cambridge, telling them that keeping “two” as an accepted answer alongside the correct one still rewarded misinformation, my complaint went to the Director of Assessment herself.
Rather than engage with the substance of my analysis, her response leaned heavily on vague language about “diverse sources” and “alternative understandings”, “rapid development of technology”, “historical context”, and “simplification”. No credible technical references were provided. Just the assertion that some websites state two transistors per cell and that some teachers may use this information to teach the course — and that, therefore, Cambridge must award marks for answering "two transistors per cell" to remain fair.
This argument fails in so many different ways, but crucially, no credible source supports the claim that flash memory uses two transistors per cell.
Not a single semiconductor manufacturer, technical standard, engineering textbook, or computer architecture course teaches this. The only places you’ll find this claim repeated are revision websites — on pages that exist solely to help students pass Cambridge exams. In other words, these sites reflect the errors baked into Cambridge’s own assessment materials and endorsed resources.
Cambridge is defending a factual error by pointing to sources that only exist because Cambridge introduced the error in the first place. It’s a self-made echo chamber — and they’re mistaking that echo for evidence.
This isn't rigour. That's anti-intellectualism, and it is unacceptable for an international exam board.
It is worth noting that they completely sidestepped the issue of NAND and NOR logic gates in every correspondence I had with them. Despite the mark scheme awarding marks for the claim that flash memory is made from logic gates, Cambridge offered no explanation, no defence, and no correction. The issue was simply ignored.
This silence speaks volumes. When confronted with an indefensible claim, Cambridge’s approach wasn’t to correct or clarify — it was to pretend the claim wasn’t made at all.
Throughout my communications with them, Cambridge repeatedly tried to reassure me by citing their “rigorous review processes”. But what are those processes worth if they lead to factually incorrect mark schemes, reinforce technical errors, and fail to engage meaningfully with feedback? That’s not rigour. That's ritual. It's performative. It’s theatre.
Fantasy Land Computer Science
To use a slightly different analogy, Cambridge Computer Science feels like it takes place in its own magical realm — much like Spirited Away. But instead of spirits and bathhouses, it’s built on misremembered concepts, empty rituals, and the belief that if enough people repeat something, it becomes true. It’s not that they’ve simplified the subject — it’s that they’ve rewritten reality to suit their own examinations. It looks vaguely like Computer Science, but it lacks the depth, coherence, and technical honesty that the discipline demands.
It's Pseudo-Computer Science... and it stinks.
Unfortunately, this wasn’t the only case of CIE misunderstanding the topics they assess. In future posts, we'll keep tugging at the bike handle...
